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4-mbit (128k x 36) pipelined sync sram cy7c1347g cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05516 rev. *e revised may 22, 2007 features ? fully registered inputs and outputs for pipelined operation ? 128k x 36 common io architecture ? 3.3v core power supply (v dd ) ? 2.5v/3.3v i/o power supply (v ddq ) ? fast clock-to-output times ? 2.6 ns (for 250-mhz device) ? user-selectable burst counter supporting intel ? pentium ? interleaved or linear burst sequences ? separate processor and controller address strobes ? synchronous self-timed writes ? asynchronous output enable ? offered in lead-free 100-pin tqfp, lead-free and non- lead-free 119-ball bga package and 165-ball fbga package ? ?zz? sleep mode option and stop clock option ? available in industrial and commercial temperature ranges functional description [1] the cy7c1347g is a 3.3v, 128k x 36 synchronous-pipelined sram designed to support zero-wait-state secondary cache with minimal glue logic. cy7c1347g io pins can operate at either the 2.5v or the 3.3v leve l; the io pins are 3.3v tolerant when v ddq = 2.5v. all synchronous inputs pass through input registers controlled by the rising edge of the clock. all data outputs pass through output registers controlled by the rising edge of the clock. maximum access delay from the clock rise is 2.6 ns (250 mhz device). cy7c1347g supports either the interleaved burst sequence us ed by the intel pentium processor or a linear burst sequence used by processors such as the powerpc ? . the burst sequence is selected through the mode pin. accesses can be initia ted by asserting either the address strobe from processor (adsp ) or the address strobe from controller (adsc ) at clock rise. address advancement through the burst sequence is controlled by the adv input. a 2-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. byte write operations are qual ified with the four byte write select (bw [a:d] ) inputs. a global write enable (gw ) overrides all byte write inputs and writes data to all four bytes. all writes are conducted with on-chip sy nchronous self-timed write circuitry. three synchronous ch ip selects (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank selection and output tri-state contro l. in order to provide proper data during depth expansion, oe is masked during the first clock of a read cycle when emerging from a deselected state. selection guide 250 mhz 200 mhz 166 mhz 133 mhz unit maximum access time 2.6 2.8 3.5 4.0 ns maximum operating current 325 265 240 225 ma maximum cmos standby current 40 40 40 40 ma note 1. for best practice recommendations, refer to the cypress application note an1064, sram system guidelines . [+] feedback [+] feedback
cy7c1347g document #: 38-05516 rev. *e page 2 of 21 logic block diagram address register adv clk burst counter and logic clr q1 q0 adsp adsc mode bwe gw ce 1 ce 2 ce 3 oe enable register output registers sense amps output buffers e pipelined enable input registers a 0, a1, a bw b bw c bw d bw a memory array dqs dqp a dqp b dqp c dqp d sleep control zz a [1:0] 2 dq a, dqp a byte write register dq b, dqp b byte write register dq c, dqp c byte write register dq d, dqp d byte write register dq a, dqp a byte write driver dq b, dqp b byte write driver dq c, dqp c byte write driver dq d ,dqp d byte write driver [+] feedback [+] feedback
cy7c1347g document #: 38-05516 rev. *e page 3 of 21 pin configurations a a a a a 1 a 0 nc/72m nc/36m v ss v dd nc/18m nc/9m a a a a a a a dqp b dq b dq b v ddq v ssq dq b dq b dq b dq b v ssq v ddq dq b dq b v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a dq a dq a v ssq v ddq dq a dq a dqp a dqp c dq c dq c v ddq v ssq dq c dq c dq c dq c v ssq v ddq dq c dq c nc v dd nc v ss dq d dq d v ddq v ssq dq d dq d dq d dq d v ssq v ddq dq d dq d dqp d a a ce 1 ce 2 bw d bw c bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode byte a byte b byte d byte c 100-pin tqfp pinout cy7c1347g [+] feedback [+] feedback
cy7c1347g document #: 38-05516 rev. *e page 4 of 21 pin configurations (continued) 2 34567 1 a b c d e f g h j k l m n p r t u v ddq nc/288m nc/144m dqp c dq c dq d dq c dq d aa aa adsp v ddq ce 2 a dq c v ddq dq c v ddq v ddq v ddq dq d dq d nc nc v ddq v dd clk v dd v ss v ss v ss v ss v ss v ss v ss v ss nc/576m nc/1g nc nc nc nc nc nc nc/36m nc/72m nc v ddq v ddq v ddq aaa a ce 3 a a a a a a a0 a1 dq a dq c dq a dq a dq a dq b dq b dq b dq b dq b dq b dq b dq a dq a dq a dq a dq b v dd dq c dq c dq c v dd dq d dq d dq d dq d adsc nc ce 1 oe adv gw v ss v ss v ss v ss v ss v ss v ss v ss dqp a mode dqp d dqp b bw b bw c nc v dd nc bw a nc bwe bw d zz 119-ball bga pinout a 165-ball fbga pinout 234 567 1 a b c d e f g h j k l m n p r nc nc/288m nc/144m dqp c dq c dqp d nc dq d ce 1bw b ce 3 bw c bwe a ce2 dq c dq d dq d mode nc dq c dq c dq d dq d dq d nc/36m nc/72m v ddq bw d bw a clk gw v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss nc/18m v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc nc v ss nc a a dq c v ss dq c v ss dq c dq c v ss v ss v ss v ss v ss v ss v ss a1 dq d dq d nc nc v ddq v ss nc 891011 nc/9m adv a adsc nc oe adsp a nc/576m v ss v ddq nc/1g dqp b v ddq v dd dq b dq b dq b nc dq b nc dq a dq a v dd v ddq v dd v ddq dq b v dd nc v dd dq a v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq dq a v ddq a a v ss a a a dq b dq b dq b zz dq a dq a dqp a dq a a v ddq a a0 a v ss [+] feedback [+] feedback
cy7c1347g document #: 38-05516 rev. *e page 5 of 21 pin definitions name io description a 0 ,a 1 ,a input- synchronous address inputs used to select one of the 128k address locations . sampled at the rising edge of the clk if adsp or adsc is active low, and ce 1 , ce 2 , and ce 3 are sampled active. a [1:0] feeds the 2-bit counter. bw a, bw b, bw c, bw d input- synchronous byte write select inputs, active low . qualified with bwe to conduct byte writes to the sram. sampled on the rising edge of clk. gw input- synchronous global write enable input, active low . when asserted low on the rising edge of clk, a global write is conducted (all bytes ar e written, regardless of the values on bw [a:d] and bwe ). bwe input- synchronous byte write enable input, active low . sampled on the rising edge of clk. this signal must be asserted low to conduct a byte write. clk input-clock clock input . used to capture all synchronous inputs to the device. also used to increment the burst counter when adv is asserted low, during a burst operation. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select or dese lect the device. adsp is ignored if ce 1 is high. ce 1 is sampled only when a new external address is loaded. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select or dese lect the device. ce 2 is sampled only when a new external address is loaded. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select or deselect the device. ce 3 is sampled only when a new external address is loaded. oe input- asynchronous output enable, asynchronous input, active low . controls the direction of the io pins. when low, the io pins behave as outputs. wh en deasserted high, io pins are tri-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. adv input- synchronous advance input signal, sampled on the rising edge of clk . when asserted, it automati- cally increments the address in a burst cycle. adsp input- synchronous address strobe from processor, sampled on the rising edge of clk . when asserted low, addresses presented to the device ar e captured in the ad dress registers. a [1:0] are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. asdp is ignored when ce 1 is deasserted high. adsc input- synchronous address strobe from controller, sampled on the rising edge of clk . when asserted low, addresses presented to the device ar e captured in the ad dress registers. a [1:0] are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. zz input- asynchronous zz ?sleep? input . this active high input places the device in a non-time-critical ?sleep? condition with data integrity preserved. during no rmal operation, this pin must be low or left floating. zz pin has an internal pull down. dq a, dq b dq c, dq d dqp a, dqp b, dqp c, dqp d io- synchronous bidirectional data io lines . as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, they deliver the data contained in the memory location specified by the addresses presented durin g the previous clock rise of the read cycle. the direction of the pins is controlled by oe . when oe is asserted low, the pins behave as outputs. when high, dqs and dqps are placed in a tri-state condition. v dd power supply power supply inputs to the core of the device . v ss ground ground for the core of the device . v ddq io power supply power supply for the io circuitry . v ssq io ground ground for the io circuitry . [+] feedback [+] feedback
cy7c1347g document #: 38-05516 rev. *e page 6 of 21 functional overview all synchronous inputs pass through input registers controlled by the rising edge of the clock. all data outputs pass through output registers controlled by the rising edge of the clock. maximum access delay fr om the clock rise (t co ) is 2.6 ns (250 mhz device). the cy7c1347g supports secondary cache in systems using either a linear or interleaved burst sequence. the linear burst sequence is suited for processo rs that utilize a linear burst sequence. the burst order is user selectable, and is deter- mined by sampling the mode i nput. accesses can be initiated with either the address st robe from processor (adsp ) or the address strobe from controller (adsc ). address advancement through the burst sequence is controlled by the adv input. a two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automati- cally increments the address for the rest of the burst access. byte write operations are qualif ied with the byte write enable (bwe ) and byte write select (bw [a:d] ) inputs. a global write enable (gw ) overrides all byte write inputs and writes data to all four bytes. all writes are simplified with on-chip synchronous self-timed write circuitry. three synchronous chip selects (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank selection and output tri-state control. adsp is ignored if ce 1 is high. single read accesses this access is initiated when the following conditions are satisfied at cloc k rise: (1) adsp or adsc is asserted low, (2) ce 1 , ce 2 , ce 3 are all asserted active, and (3) the write signals (gw , bwe ) are all deasserted high. adsp is ignored if ce 1 is high. the address presented to the address inputs (a [16:0] ) is stored into the address advancement logic and the address register while being presented to the memory core. the corre- sponding data is allowed to propagate to the input of the output registers. at the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 2.6 ns (250 mhz device) if oe is active low. the only exception occurs when the sram is emerging from a deselected state to a selected state, its outputs are always tri-stated during the firs t cycle of the access. after the first cycle of the access, the ou tputs are controlled by the oe signal. consecutive single read cycles are supported. after the sram is deselected at clock rise by the chip select and either adsp or adsc signals, its output tri-states immediately. single write accesses initiated by adsp this access is initiated when both of the following conditions are satisfied at clock rise: (1) adsp is asserted low, and (2) ce 1 , ce 2 , ce 3 are all asserted active. the address presented to a [16:0] is loaded into the address register and the address advancement logic while being delivered to the ram core. the write signals (gw , bwe , and bw [a:d] ) and adv inputs are ignored during th is first cycle. adsp -triggered write accesses re quire two clock cycles to complete. if gw is asserted low on the second clock rise, the data presented to the dqs and dqps inputs is written into the corresponding address location in the ram core. if gw is high, then the write operation is controlled by bwe and bw [a:d] signals. the cy7c1347g provides byte write capability that is described in ?partial truth table for read/write? on page 9 . asserting the byte write enable input (bwe ) with the selected byte write (bw [a:d] ) input selectively writes to only the desired bytes. bytes not selected during a byte write operation remain unaltered. a synchronous self -timed write mechanism has been provided to simplify the write operations. because the cy7c1347g is a common io device, the output enable (oe ) must be deasserted high before presenting data to the dqs and dqps inputs. doing so tri-states the output drivers. as a safety precauti on, dqs and dqps are automati- cally tri-stated whenever a writ e cycle is detected, regardless of the state of oe . single write accesses initiated by adsc adsc write accesses are initiated when the following condi- tions are satisfied: (1) adsc is asserted low, (2) adsp is deasserted high, (3) ce 1 , ce 2 , ce 3 are all asserted active, and (4) the appropriate combination of the write inputs (gw , bwe , and bw [a:d] ) are asserted active to conduct a write to the desired byte(s). adsc -triggered write accesses require a single clock cycle to comple te. the address presented to a [16:0] is loaded into the address register and the address advancement logic while being delivered to the ram core. the adv input is ignored during this cycle. if a global write is conducted, the data presented to the dqs and dqps is written into the corresponding address location in the ram core. if a byte write is conducted, only the selected bytes are written. bytes not selected during a byte write operation remain unaltered. a synchronous self -timed write mechanism has been provided to simplify the write operations. because the cy7c1347g is a common io device, the output enable (oe ) must be deasserted high before presenting data mode input- static selects burst order . when tied to gnd selects linear burst sequence. when tied to v ddq or left floating selects interleaved burst sequence. this is a strap pin and must remain static during device operation. mode pin has an internal pull up. nc, nc/9m, nc/18m, nc/36m, nc/72m, nc/144m, nc/288m, nc/576m, nc/1g ? no connects . not internally connected to th e die. nc/9m, nc/18m , nc/36m, nc/72m, nc/144m, nc/288m, nc/576m, and nc/ 1g are address expansion pins that are not inter- nally connected to the die. pin definitions (continued) name io description [+] feedback [+] feedback
cy7c1347g document #: 38-05516 rev. *e page 7 of 21 to the dqs and dqps inputs. doing so tri-states the output drivers. as a safety precauti on, dqs and dqps are automati- cally tri-stated whenever a wr ite cycle is dete cted, regardless of the state of oe . burst sequences the cy7c1347g provides a two-bit wraparound counter, fed by a [1:0] , that implements either an interleaved or linear burst sequence. the interleaved burst sequence is designed specif- ically to support intel pentium applications. the linear burst sequence is designed to support processors that follow a linear burst sequence. the burst sequence is user-selectable through the mode input. asserting adv low at clock rise autom atically increments the burst counter to the next addre ss in the burst sequence. both read and write burst operations are supported. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, da ta integrity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected before entering the ?sleep? mode. ce 1 , ce 2 , ce 3 , adsp , and adsc must remain inactive for the duration of t zzrec after the zz input returns low. interleaved burst sequence first address second address third address fourth address a [1:0] a [1:0] a [1:0] a [1:0] 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst sequence first address second address third address fourth address a [1:0] a [1:0] a [1:0] a [1:0] 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min max unit i ddzz snooze mode standby current zz > v dd ? 0.2v 40 ma t zzs device operation to zz zz > v dd ? 0.2v 2t cyc ns t zzrec zz recovery time zz < 0.2v 2t cyc ns t zzi zz active to snooze current this parameter is sampled 2t cyc ns t rzzi zz inactive to exit snooze cu rrent this parameter is sampled 0 ns [+] feedback [+] feedback
cy7c1347g document #: 38-05516 rev. *e page 8 of 21 truth table the truth table for cy7c1347g follows. [2, 3, 4, 5, 6] next cycle add. used ce 1 ce 2 ce 3 zz adsp adsc adv write oe clk dq deselect cycle, power down none h x x l x l x x x l-h tri-state deselect cycle, power down none l l x l l x x x x l-h tri-state deselect cycle, power down none l x h l l x x x x l-h tri-state deselect cycle, power down none l l x l h l x x x l-h tri-state deselect cycle, power down none l x h l h l x x x l-h tri-state snooze mode, power down none x x x h x x x x x x tri-state read cycle, begin burst external l h l l l x x x l l-h q read cycle, begin burst external l h l l l x x x h l-h tri-state write cycle, begin burst external l h l l h l x l x l-h d read cycle, begin burst external l h l l h l x h l l-h q read cycle, begin burst external l h l l h l x h h l-h tri-state read cycle, continue burst next x x x l h h l h h l-h tri-state read cycle, continue burst next x x x l h h l h l l-h q read cycle, continue burst next h x x l x h l h l l-h q read cycle, continue burst next h x x l x h l h h l-h tri-state write cycle, continue burst next x x x l h h l l x l-h d write cycle, continue burst next h x x l x h l l x l-h d read cycle, suspend burst current x x x l h h h h l l-h q read cycle, suspend burst current x x x l h h h h h l-h tri-state read cycle, suspend burst current h x x l x h h h l l-h q read cycle, suspend burst current h x x l x h h h h l-h tri-state write cycle, suspend burst current x x x l h h h l x l-h d write cycle, suspend burst current h x x l x h h l x l-h d notes: 2. x = ?do not care.? h = logic high, l = logic low. 3. write = l when any one or more byte write enable signals (bw a , bw b , bw c , bw d ) and bwe = l or gw = l. write = h when all byte write enable signals (bw a , bw b , bw c , bw d ), bwe , gw = h. 4. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 5. the sram always initiates a read cycle when adsp is asserted, regardless of the state of gw , bwe , or bw [a:d] . writes may occur only on subsequent clocks after the adsp or with the assertion of adsc . as a result, oe must be driven high before the start of the write cycle to allow the outputs to tri-state. oe is a don't care for the remai nder of the write cycle. 6. oe is asynchronous and is not sampled with the clock rise. it is masked internally during writ e cycles. during a read cycle all d ata bits are tri-state when oe is inactive or when the device is deselected, and all data bits behave as output when oe is active (low). [+] feedback [+] feedback
cy7c1347g document #: 38-05516 rev. *e page 9 of 21 partial truth table for read/write the partial read/write truth table for cy7c1347g follows. [2, 7] function gw bwe bw d bw c bw b bw a read hhxxxx read hlhhhh write byte a ? dq a hlhhhl write byte b ? dq b hlhhlh write bytes b, a h l h h l l write byte c? dq c hlhlhh write bytes c, a h l h l h l write bytes c, b h l h l l h write bytes c, b, a h l h l l l write byte d? dq d hl lhhh write bytes d, a h l l h h l write bytes d, b h l l h l h write bytes d, b, a h l l h l l write bytes d, c h l l l h h write bytes d, c, a h l l l h l write bytes d, c, b hllllh write all bytes hlllll write all bytes lxxxxx note 7. table is only a partial listing of the byte write combinations. any combination of bw x is valid. appropriate write is based on which byte write is active. [+] feedback [+] feedback
cy7c1347g document #: 38-05516 rev. *e page 10 of 21 maximum ratings exceeding the maximum ratings may shorten the battery life of the device. user guidelines are not tested. storage temperature ..................................... ? 65 c to +150 c ambient temperature with power applied .................................................. ? 55 c to +125 c supply voltage on v dd relative to gnd .........? 0.5v to +4.6v supply voltage on v ddq relative to gnd .......? 0.5v to +v dd dc voltage applied to outputs in high-z state ........................................... ? 0.5v to v dd + 0.5v dc input voltage ....................................... ? 0.5v to v dd + 0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... ........... ............ .......... > 2001v (mil-std-883, method 3015) latch up current ................................................... > 200 ma operating range range ambient temperature v dd v ddq commercial 0c to +70c 3.3v ? 5%/+10% 2.5v ? 5% to v dd industrial ?40c to +85c electrical characteristics over the operating range [8, 9] parameter description test conditions min max unit v dd power supply voltage 3.135 3.6 v v ddq io supply voltage 2.375 v dd v v oh output high voltage for 3.3v io, i oh = ?4.0 ma 2.4 v for 2.5v io, i oh = ?1.0 ma 2.0 v v ol output low voltage for 3.3v io, i ol = 8.0 ma 0.4 v for 2.5v io, i ol = 1.0 ma 0.4 v v ih input high voltage [8] for 3.3v io 2.0 v dd + 0.3v v for 2.5v io 1.7 v dd + 0.3v v v il input low voltage [8] for 3.3v io ?0.3 0.8 v for 2.5v io ?0.3 0.7 v i x input leakage current except zz and mode gnd < v i < v ddq ? 5 5 a input current of mode input = v ss ? 30 a input = v dd 5 a input current of zz input = v ss ? 5 a input = v dd 30 a i oz output leakage current gnd v i v ddq, output disabled ? 5 5 a i dd v dd operating supply current v dd = max., i out = 0 ma, f = f max = 1/t cyc 4-ns cycle, 250 mhz 325 ma 5-ns cycle, 200 mhz 265 ma 6-ns cycle, 166 mhz 240 ma 7.5-ns cycle, 133 mhz 225 ma i sb1 automatic ce power down current?ttl inputs max. v dd , device deselected, v in > v ih or v in < v il f = f max = 1/t cyc 4-ns cycle, 250 mhz 120 ma 5-ns cycle, 200 mhz 110 ma 6-ns cycle, 166 mhz 100 ma 7.5-ns cycle, 133 mhz 90 ma i sb2 automatic ce power down current?cmos inputs max. v dd , device deselected, v in < 0.3v or v in > v ddq ? 0.3v, f = 0 all speeds 40 ma notes 8. overshoot: v ih (ac) < v dd +1.5v (pulse width less than t cyc /2). undershoot: v il (ac) > ?2v (pulse width less than t cyc /2). 9. t power-up : assumes a linear ramp from 0v to v dd (min) within 200 ms. during this time v ih < v dd and v ddq < v dd . [+] feedback [+] feedback
cy7c1347g document #: 38-05516 rev. *e page 11 of 21 i sb3 automatic ce power down current?cmos inputs max. v dd , device deselected, or v in < 0.3v or v in > v ddq ? 0.3v f = f max = 1/t cyc 4-ns cycle, 250 mhz 105 ma 5-ns cycle, 200 mhz 95 ma 6-ns cycle, 166 mhz 85 ma 7.5-ns cycle, 133 mhz 75 ma i sb4 automatic ce power down current?ttl inputs max. v dd , device deselected, v in v ih or v in v il , f = 0 45 ma electrical characteristics over the operating range (continued) [8, 9] parameter description test conditions min max unit capacitance tested initially and after any design or proces s changes that may affect these parameters. parameter description test conditions 100 tqfp max 119 bga max 165 fbga max unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 3.3v. v ddq = 3.3v 5 5 5 pf c clk clock input capacitance 5 5 5 pf c io input/output capacitance 5 7 7 pf thermal resistance tested initially and after any design or proces s changes that may affect these parameters. parameter description test conditions 100 tqfp package 119 bga package 165 fbga package unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. 30.32 34.1 20.3 c/w jc thermal resistance (junction to case) 6.85 14.0 4.6 c/w ac test loads and waveforms figure 1. ac test loads and waveforms output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? 3.3v all input pulses v ddq gnd 90% 10% 90% 10% 1 ns 1 ns (c) output r = 1667 ? r = 1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.25v 2.5v all input pulses v ddq gnd 90% 10% 90% 10% 1 ns 1 ns (c) 3.3v i/o test load 2.5v i/o test load v t = 1.5v [+] feedback [+] feedback
cy7c1347g document #: 38-05516 rev. *e page 12 of 21 switching characteristics over the operating range [14, 15] parameter description ?250 ?200 ?166 ?133 unit min max min max min max min max t power v dd (typical) to the first access [10] 11 11ms clock t cyc clock cycle time 4.0 5.0 6.0 7.5 ns t ch clock high 1.7 2.0 2.5 3.0 ns t cl clock low 1.7 2.0 2.5 3.0 ns output times t co data output valid after clk rise 2.6 2.8 3.5 4.0 ns t doh data output hold after clk rise 1.0 1.0 1.5 1.5 ns t clz clock to low-z [11, 12, 13] 00 00ns t chz clock to high-z [11, 12, 13] 2.6 2.8 3.5 4.0 ns t oev oe low to output valid 2.6 2.8 3.5 4.5 ns t oelz oe low to output low-z [11, 12, 13] 00 00ns t oehz oe high to output high-z [11, 12, 13] 2.6 2.8 3.5 4.0 ns setup times t as address setup before clk rise 1.2 1.2 1.5 1.5 ns t ads adsc , adsp setup before clk rise 1.2 1.2 1.5 1.5 ns t advs adv setup before clk rise 1.2 1.2 1.5 1.5 ns t wes gw , bwe , bw x setup before clk rise 1.2 1.2 1.5 1.5 ns t ds data input setup before clk rise 1.2 1.2 1.5 1.5 ns t ces chip enable setup before clk rise 1.2 1.2 1.5 1.5 ns hold times t ah address hold after clk rise 0.3 0.5 0.5 0.5 ns t adh adsp , adsc hold after clk rise 0.3 0.5 0.5 0.5 ns t advh adv hold after clk rise 0.3 0.5 0.5 0.5 ns t weh gw , bwe , bw x hold after clk rise 0.3 0.5 0.5 0.5 ns t dh data input hold after clk rise 0.3 0.5 0.5 0.5 ns t ceh chip enable hold after clk rise 0.3 0.5 0.5 0.5 ns notes 10. this part has an internal voltage regulator; t power is the time that the power must be supplied above v dd (min) initially before a read or write operation can be initiated. 11. t chz , t clz , t oelz , and t oehz are specified with ac test conditions shown in part (b) of ?ac test loads and waveforms? on page 11 . transition is measured 200 mv from steady-state voltage. 12. at any voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user condi tions. device is designed to achieve high-z prior to low-z under the same system conditions. 13. this parameter is sampled and not 100% tested. 14. timing references level is 1.5v when v ddq = 3.3v and is 1.25v when v ddq = 2.5v on all data sheets. 15. test conditions shown in (a) of ?ac test loads and waveforms? on page 11 unless otherwise noted. [+] feedback [+] feedback
cy7c1347g document #: 38-05516 rev. *e page 13 of 21 switching waveforms figure 2 shows read cycle timing waveforms. [16] figure 2. read cycle timing t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces gw, bwe, bw [a:d] data out (q) high-z t clz t doh t co adv t oehz t co single read burst read t oev t oelz t chz adv suspends burst. burst wraps around to its initial state t advh t advs t weh t wes t adh t ads q(a2) q(a2 + 1) q(a2 + 2) q(a1) q(a2) q(a2 + 1) q(a2 + 3) a2 a3 deselect cycle burst continued with new base address dont care undefined note 16. on this diagram, when ce is low, ce 1 is low, ce 2 is high, and ce 3 is low. when ce is high, ce 1 is high, ce 2 is low, or ce 3 is high. [+] feedback [+] feedback
cy7c1347g document #: 38-05516 rev. *e page 14 of 21 figure 3 shows write cycle timing waveforms. [16, 17] figure 3. write cycle timing switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces bwe, bw[a :b] data out (q) high-z adv burst read burst write d(a2) d(a2 + 1) d(a2 + 1) d(a1) d(a3) d(a3 + 1) d(a3 + 2) d(a2 + 3) a2 a3 data in (d) extended burst write d(a2 + 2) single write t adh t ads t adh t ads t oehz t advh t advs t weh t wes t dh t ds gw t weh t wes byte write signals are ignored for rst cycle when adsp initiates burst adsc extends burst adv suspends burst dont care undefined note 17. full width write can be initiated by either gw low, or by gw high, bwe low, and bw x low. [+] feedback [+] feedback
cy7c1347g document #: 38-05516 rev. *e page 15 of 21 figure 4 shows read/write cycle timing waveforms. [16, 18, 19] figure 4. read/write cycle timing switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a2 t ceh t ces bwe, bw[a:d] data out (q) high-z adv single write d(a3) a4 a5 a6 d(a5) d(a6) data in (d) burst read back-to-back reads high-z q(a2) q(a1) q(a4) q(a4+1) q(a4+2) t weh t wes q(a4+3) t oehz t dh t ds t oelz t clz t co back-to-back writes a1 dont care undefined a3 notes 18. the data bus (q) remains in high-z following a write cycle, unless a new read access is initiated by adsp or adsc . 19. gw is high. [+] feedback [+] feedback
cy7c1347g document #: 38-05516 rev. *e page 16 of 21 figure 5 shows zz mode timing waveforms. [20, 21] figure 5. zz mode timing switching waveforms (continued) t zz i supply clk zz t zzrec a ll inputs (except zz) dont care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only notes 20. device must be deselected when entering zz mode. see ?truth table? on page 8 for all possible signal conditions to deselect the device. 21. dqs are in high-z when exiting zz sleep mode. [+] feedback [+] feedback
cy7c1347g document #: 38-05516 rev. *e page 17 of 21 ordering information not all of the speed, package and temperature ranges are availa ble. please contact your local sales representative or visit www.cypress.com for actual products offered. speed (mhz) ordering code package diagram package type operating range 133 cy7c1347g-133axc 51-85050 100-pin thin quad flat pack (1 4 x 20 x 1.4 mm) pb-free commercial cy7c1347g-133bgc 51-85115 119-ball ball grid array (14 x 22 x 2.4 mm) cy7c1347g-133bgxc 119-ball ball grid array (14 x 22 x 2.4 mm) pb-free cy7c1347g-133bzc 51-85180 165-ball fine-pitch ball grid array (13 x 15 x 1.4 mm) cy7c1347g-133bzxc 165-ball fine-pitch ball grid array (13 x 15 x 1.4 mm) pb-free cy7c1347g-133axi 51-85050 1 00-pin thin quad flat pack (14 x 20 x 1.4 mm) pb-free industrial cy7c1347g-133bgi 51-85115 119-ball ball grid array (14 x 22 x 2.4 mm) cy7c1347g-133bgxi 119-ball ball grid array (14 x 22 x 2.4 mm) pb-free cy7c1347g-133bzi 51-85180 165-ball fine-pitch ball grid array (13 x 15 x 1.4 mm) cy7c1347g-133bzxi 165-ball fine-pitch ball grid array (13 x 15 x 1.4 mm) pb-free 166 cy7c1347g-166axc 51-85050 100-pin thin quad flat pack (1 4 x 20 x 1.4 mm) pb-free commercial cy7c1347g-166bgc 51-85115 119-ball ball grid array (14 x 22 x 2.4 mm) cy7c1347g-166bgxc 119-ball ball grid array (14 x 22 x 2.4 mm) pb-free cy7c1347g-166bzc 51-85180 165-ball fine-pitch ball grid array (13 x 15 x 1.4 mm) cy7c1347g-166bzxc 165-ball fine-pitch ball grid array (13 x 15 x 1.4 mm) pb-free cy7c1347g-166axi 51-85050 1 00-pin thin quad flat pack (14 x 20 x 1.4 mm) pb-free industrial cy7c1347g-166bgi 51-85115 119-ball ball grid array (14 x 22 x 2.4 mm) cy7c1347g-166bgxi 119-ball ball grid array (14 x 22 x 2.4 mm) pb-free cy7c1347g-166bzi 51-85180 165-ball fine-pitch ball grid array (13 x 15 x 1.4 mm) cy7c1347g-166bzxi 165-ball fine-pitch ball grid array (13 x 15 x 1.4 mm) pb-free 200 CY7C1347G-200AXC 51-85050 100-pin thin quad flat pack (1 4 x 20 x 1.4 mm) pb-free commercial cy7c1347g-200bgc 51-85115 119-ball ball grid array (14 x 22 x 2.4 mm) cy7c1347g-200bgxc 119-ball ball grid array (14 x 22 x 2.4 mm) pb-free cy7c1347g-200bzc 51-85180 165-ball fine-pitch ball grid array (13 x 15 x 1.4 mm) cy7c1347g-200bzxc 165-ball fine-pitch ball grid array (13 x 15 x 1.4 mm) pb-free cy7c1347g-200axi 51-85050 1 00-pin thin quad flat pack (14 x 20 x 1.4 mm) pb-free industrial cy7c1347g-200bgi 51-85115 119-ball ball grid array (14 x 22 x 2.4 mm) cy7c1347g-200bgxi 119-ball ball grid array (14 x 22 x 2.4 mm) pb-free cy7c1347g-200bzi 51-85180 165-ball fine-pitch ball grid array (13 x 15 x 1.4 mm) cy7c1347g-200bzxi 165-ball fine-pitch ball grid array (13 x 15 x 1.4 mm) pb-free 250 cy7c1347g-250axc 51-85050 100-pin thin quad flat pack (1 4 x 20 x 1.4 mm) pb-free commercial cy7c1347g-250bgc 51-85115 119-ball ball grid array (14 x 22 x 2.4 mm) cy7c1347g-250bgxc 119-ball ball grid array (14 x 22 x 2.4 mm) pb-free cy7c1347g-250bzc 51-85180 165-ball fine-pitch ball grid array (13 x 15 x 1.4 mm) cy7c1347g-250bzxc 165-ball fine-pitch ball grid array (13 x 15 x 1.4 mm) pb-free cy7c1347g-250axi 51-85050 1 00-pin thin quad flat pack (14 x 20 x 1.4 mm) pb-free industrial cy7c1347g-250bgi 51-85115 119-ball ball grid array (14 x 22 x 2.4 mm) cy7c1347g-250bgxi 119-ball ball grid array (14 x 22 x 2.4 mm) pb-free cy7c1347g-250bzi 51-85180 165-ball fine-pitch ball grid array (13 x 15 x 1.4 mm) cy7c1347g-250bzxi 165-ball fine-pitch ball grid array (13 x 15 x 1.4 mm) pb-free [+] feedback [+] feedback
cy7c1347g document #: 38-05516 rev. *e page 18 of 21 package diagrams figure 6. 100-pin thin plastic quad flatpack (14 x 20 x 1.4 mm), 51-85050 note: 1. jedec std ref ms-026 2. body length dimension does not include mold protrusion/end flash mold protrusion/end flash shall not exceed 0.0098 in (0.25 mm) per side 3. dimensions in millimeters body length dimensions are max plastic body size including mold mismatch 0.300.08 0.65 20.000.10 22.000.20 1.400.05 121 1.60 max. 0.05 min. 0.600.15 0 min. 0.25 0-7 (8x) stand-off r 0.08 min. typ. 0.20 max. 0.15 max. 0.20 max. r 0.08 min. 0.20 max. 14.000.10 16.000.20 0.10 see detail a detail a 1 100 30 0 5 1 3 51 80 81 gauge plane 1.00 ref. 0.20 min. seating plane 51-85050-*b [+] feedback [+] feedback
cy7c1347g document #: 38-05516 rev. *e page 19 of 21 figure 7. 119-ball bga (14 x 22 x 2.4 mm), 51-85115 package diagrams (continued) 51-85115-*b [+] feedback [+] feedback
cy7c1347g document #: 38-05516 rev. *e page 20 of 21 ? cypress semiconductor corporation, 2004-2007. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent o r other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. intel and pentium are registered trademarks of intel corporation. powerpc is a registered trademark of international business m achines, inc. all product and company names mentioned in this document may be the trademarks of their respective holders. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions. cypress hereby grants to licensee a personal, non-e xclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the so le purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, tran slation, compilation, or representation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or im plied, with regard to this mate rial, including, but not limited to, the implied war- ranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further not ice to the materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. figure 8. 165-ball fbga (13 x 15 x 1.4 mm), 51-85180 package diagrams (continued) a 1 pin 1 corner 15.000.10 13.000.10 7.00 1.00 ?0.50 (165x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.350.06 seating plane 0.530.05 0.25 c 0.15 c pin 1 corner top view bottom view 2 3 4 5 6 7 8 9 10 10.00 14.00 b c d e f g h j k l m n 11 11 10 9 8 67 5 4 3 2 1 p r p r k m n l j h g f e d c b a a 15.000.10 13.000.10 b c 1.00 5.00 0.36 - 0.06 +0.14 1.40 max. solder pad type : non-solder mask defined (nsmd) notes : package weight : 0.475g jedec reference : mo-216 / design 4.6c package code : bb0ac 51-85180-*a [+] feedback [+] feedback
cy7c1347g document #: 38-05516 rev. *e page 21 of 21 document history page document title: cy7c1347g 4-mbit (128k x 36) pipelined sync sram document number: 38-05516 rev. ecn no. issue date orig. of change description of change ** 224364 see ecn rkf new data sheet *a 276690 see ecn vbl changed tqfp package in ordering information section to lead-free tqfp added comment of bg and bz lead-free package availability *b 333625 see ecn syt removed 225-mhz and 100-mhz speed grades modified address expansion balls in the pinouts for 100 tqfp package as per jedec standards and updated the pin definitions accordingly modified v ol, v oh test conditions replaced tbds for ja and jc to their respective values on the thermal resis- tance table changed the package name for 100 tqfp from a100ra to a101 removed comment on the availability of bg lead-free package updated the ordering information by shading and unshading mpns as per availability *c 419256 see ecn rxu converted from preliminary to final. changed address of cypress semiconductor corporation on page #1 from ?3901 north first street? to ?198 champion court? swapped typo ce 2 and ce 3 in the truth table column heading on page #6 modified test condition from v ih < v dd to v ih < v dd. modified test condition from v ddq < v dd to v ddq < v dd modified ?input load? to ?input leakage current except zz and mode? in the electrical characteristics table. replaced package name column with package diagram in the ordering infor- mation table. replaced package diagram of 51-85050 from *a to *b replaced package diagram of 51-85180 from ** to *a updated the ordering information. *d 480124 see ecn vkn added the maximum rating for supply voltage on v ddq relative to gnd. updated the ordering information table. *e 1078184 see ecn vkn corrected write timing diagram on page 12 [+] feedback [+] feedback

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